> ls -la ./projects

THE BUILD
LOG

ALL · 06 FPGA IoT WEB MOBILE SECURITY
FPGA · CRYPTO IP001
[ IMG: waveform / DPA trace ]
Constant-Time AES Core

Masked-S-box AES-256 IP hardened against differential power analysis, verified on a low-cost Artix-7. Constant-time by construction; leakage assessed with TVLA.

VerilogVivadoTVLA
read case study →
IoT · EMBEDDED002
[ IMG: feeder cam rig ]
Solar Bird-Feeder Cam

Solar-powered ESP32-S3 that wakes on motion, runs an on-device species classifier, and syncs sightings to a self-hosted field journal over LoRa.

ESP32-S3TinyMLLoRa
read case study →
SECURITY · RTL003
[ IMG: locked netlist graph ]
Logic-Lock Toolkit

Open CLI that inserts key-gated logic locking into a gate-level netlist, then scores its resilience against SAT-based attacks. Batteries and datasheet included.

PythonYosysSAT
read case study →
MOBILE · GPS004
[ IMG: trail map UI ]
Trailhead Offline

Offline-first hiking companion — vector topo caching, campsite pins, and a dawn-chorus alarm that wakes you for peak bird activity. No signal required.

SwiftKotlinMapLibre
read case study →
WEB · TOOLING005
[ IMG: waveform viewer ]
WavePeek

Browser-based VCD/FST waveform viewer that renders million-transition traces at 60fps using a WebGL2 renderer and a streaming parser. Built for RTL debugging.

TypeScriptWebGL2WASM
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FPGA · RETRO006
[ IMG: CRT + soft-core ]
6502 On A Breadboard-FPGA

A cycle-accurate 6502 soft-core with a VGA text-mode framebuffer, driving a real CRT. Boots a tiny monitor ROM and blinks its own status LEDs. Pure nostalgia.

SystemVerilogVGA6502
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